Job Description

- NAND verilog behavior modeling
- verilog modeling for analog/pagebufferlay cell
- usermode fullchip function verification
- testmode fullchip function check

Required People：Several

Job Description

- standard cell 
- Verilog design and systhesis
- block design and simulation
  . Usermode READ/PGM/ERASE/RESET algorithm/sequence and timing control
  . HV control
  . CAM operation sequence 
  . Command decoder
  . ECC encoder/decoder
  . Address counter
  . Testmode entry/exit sequence and algorithm
  . trimming/bad blk/otp blk config register array
- Fullchip function check

Required People：Several

Job Description

'- standard cell
- PDK analysis
- HV/X-path architecture
- Cell array architecture for block(Main, block 0 replace, CAM block, otp)(/page
- power-up sequence
- block design and simulation
  . POR/PDR
  . BGR
  . LDO
  . Oscillator
  . OPAMP
  . config register
  . High voltage pump and HV switch
  . Regulator for pagebuffer control
  . Regulator for X-Path control
  . X-path control and x-decoder
  . Testmode(BIST, Stress mode) for analog and X-path
- Fullchip function check
- Standby current check

Required People：Several